Metallization arrangement for semiconductor structure and corresponding fabrication method

ABSTRACT

The present invention provides a metallization arrangement for a semiconductor structure ( 1 ) having a first substructure plane (M 1 ), preferably a first metallization plane; a second metallization plane (M 2 ) having a first and a second adjacent interconnect (LBA; LBB); a first intermediate dielectric (ILD 1 ) for mutual electrical insulation of the first substructure plane (M 1 ) and second metallization plane (M 2 ); and via holes (V) filled with a conductive material (FM) in the intermediate dielectric (ILD 1 ) for connecting the first substructure plane (M 1 ) and second metallization plane (M 2 ). A liner layer (L) made of a dielectric material is provided under the second metallization plane (M 2 ), which liner layer is interrupted in the interspace (O) between the first and second adjacent interconnects (LBA; LBB) of the second metallization plane (M 2 ). The invention likewise provides a corresponding fabrication method.

DESCRIPTION

[0001] The present invention relates to a metallization arrangement fora semiconductor structure having a first substructure plane; a secondmetallization plane having a first and a second adjacent interconnect; afirst intermediate dielectric for mutual electrical insulation of thefirst substructure plane and second metallization lane; and via holesfilled with a conductive material in the first intermediate dielectricfor connecting the first substructure plane and second metallizationplane. The invention likewise relates to a corresponding fabricationmethod.

[0002] The term semiconductor structure is to be understood in thegeneral sense and can therefore encompass both single-layered andmultilayered structures with any desired semiconductor components. Byway of example, the semiconductor structure is an integrated circuit forwhich the metallization arrangement provides internal or externalwiring.

[0003]FIG. 2 shows a diagrammatic illustration of a known metallizationarrangement for a semiconductor structure.

[0004] In FIG. 2, 1 designates a semiconductor structure, for example anelectrical circuit integrated in a silicon substrate, L1 designates afirst liner layer made of silicon dioxide, M1 designates a firstmetallization plane, ILD designates an intermediate dielectric, Vdesignates a via hole filled with a conductive material FM, L2designates a second liner layer, M2 designates a second metallizationlayer, LBA designates a first interconnect, LBB designates a secondinterconnect and O designates an interspace between the first and secondinterconnects LBA, LBB, and K designates critical locations of thestructure.

[0005] In general, the aim of introducing the intermediate dielectricILD having a low dielectric constant is to reduce the capacitivecoupling of adjacent interconnects and thus improve the functionalefficiency with the chip are unchanged. However, integrating theintermediate dielectric ILD having a low dielectric constant generallyrequires the provision of the liner layer L1 or L2, for example in theform of a silicon oxide liner or silicon nitride liner, for patterningthe via holes V and as diffusion barrier (e.g. in the case of ALCumetallization).

[0006] The relatively high dielectric constant of such a liner layer L1or L2 in the form of a silicon oxide liner or silicon nitride liner hasan adverse effect, however, on the capacitive coupling of adjacentinterconnects, for example LBA and LBB. Such critical locations in theknown arrangement in accordance with FIG. 2 are designated by K.

[0007] The present invention is based on the object of reducing thedisturbing capacitive coupling.

[0008] According to the invention, this object is achieved by means ofthe semiconductor component specified in claim 1 and the fabricationmethod specified in claim 6.

[0009] According to the present invention, it is possible toconsiderably reduce disturbing capacitive coupling between adjacentinterconnects of the second metallization plane.

[0010] The general idea underlying the present invention is that a linerlayer made of a dielectric material is provided under the secondmetallization plane, which liner layer is interrupted in the interspacebetween the first and second adjacent interconnects of the secondmetallization plane.

[0011] The subclaims contain advantageous developments and improvementsof the semiconductor component specified in claim 1 and, respectively,of the fabrication method specified in claim 7.

[0012] In accordance with a preferred development, the firstsubstructure plane is a first metallization plane.

[0013] In accordance with a further preferred development, theinterspace between the first and second adjacent interconnects of thesecond metallization plane is filled with a second intermediatedielectric above the first intermediate dielectric. Thus, it is possiblefor a plurality of metallization layers with intervening dielectrics tobe stacked one above the other.

[0014] In accordance with a further preferred development, thesemiconductor structure has an electrical circuit integrated in asilicon substrate.

[0015] In accordance with a further preferred development, the linerlayer is fabricated from silicon dioxide or silicon nitride.

[0016] In accordance with a further preferred development, the firstand/or second metallization plane are/is fabricated from ALCu.

[0017] In accordance with a further preferred development, thepatterning and interrupting are carried out in a common etching step.This requires merely the selection of a suitable etchant and/or of asuitable liner/metal combination. In comparison with the customaryprocess, there is then merely a need for a longer etching time, but notfor an additional mask plane or an additional etching step.

[0018] In accordance with a further preferred development, thepatterning is carried out in a first metal etching step and theinterrupting is carried out in a second silicon dioxide etching step.

[0019] In accordance with a further preferred development, a hard maskor a resist mask, which is provided on the second metallization plane,is used for the patterning and interrupting processes.

[0020] An exemplary embodiment of the invention is illustrated in thedrawings and explained in more detail in the description below.

[0021]FIGS. 1a-h show a diagrammatic illustration of the essentialmethod steps for fabricating a metallization arrangement for asemiconductor structure as embodiment of the present invention; and

[0022]FIG. 2 shows a diagrammatic illustration of a known metallizationarrangement of a semiconductor structure.

[0023] In the figures, identical reference symbols designate identicalor functionally identical elements.

[0024]FIGS. 1a-h show a diagrammatic illustration of the essentialmethod steps for fabricating a metallization arrangement for asemiconductor structure as embodiment of the present invention.

[0025] As illustrated in FIG. 1a, first of all the first metallizationlayer M1 is deposited on the semiconductor structure 1 and patterned.Afterward, an intermediate dielectric ILD1 is deposited over the wholearea on the resulting structure. This intermediate dielectric ILD1having a low dielectric constant is a carbon-containing SiO₂ layer, forexample.

[0026] According to FIG. 1b, in a following process step, a liner layerL is applied to the resulting structure. In this respect, it should benoted that the dielectric constant of the liner layer L is greater thanthe dielectric constant of the intermediate dielectric ILD1.

[0027] The liner layer L and the intermediate dielectric ILD1 are thenpatterned by means of a standard photolithographic technique. Thiscreates the via hole V, as illustrated in FIG. 1c.

[0028] In a further process step, as illustrated in FIG. 1d, the viahole V is then filled with the conductive filling material FM.

[0029] Afterward, or in the same process step, a second metallizationlayer M2 is then deposited, which leads to the structure shown in FIG.1e.

[0030] A photoresist mask or, as in the present example, a hard maskmade of silicon nitride, for example, is subsequently provided on thesecond metallization layer M2. Using the hard mask HM, the secondmetallization layer M2 is patterned into the interconnects LBA and LBB.This is illustrated in FIG. 1f.

[0031] Either in the same etching step or in an additional etching stepusing a different etching medium, the uncovered liner layer L is thenetched away, with the result that the interspace O no longer containsany liner nor any metal. This is illustrated in FIG. 1g.

[0032] Consequently, the metal structure transferred to the liner layerL made of silicon dioxide. Given suitable selection of the liner layer 6and of the etching medium, this merely requires prolonging the knownetching process for the metallization layer M2.

[0033] In accordance with the structure illustrated in FIG. 1h, the hardmask HM is then removed and a further intermediate dielectric layer ILD2is deposited. Either a concluding passivation layer or a further thirdmetallization layer, etc, can then be applied on said furtherintermediate dielectric ILD2.

[0034] As can clearly be seen from FIG. 1h, this type of process controlresults in the liner layer L made of silicon dioxide being removedwherever the metal layer M2 is also removed, with the result that thedisturbing capacitive coupling effects are eliminated.

[0035] Although the present invention has been described above using apreferred exemplary embodiment, it is not restricted thereto but rathercan be modified in diverse ways.

[0036] It goes without saying that the present invention can be appliedto any desired semiconductor structures, in particular integratedcircuits, and any desired basic semiconductor materials; in particular,it is possible to use any desired semiconductor materials or materialsandwiches as substrates.

[0037] Although the first substructure plane is a metallization plane inthe above example, it can also be a different plane, that is to say theinvention can be applied to the bottommost metallization plane.

1. A metallization, arrangement or a semiconductor structure (1) having:a first substructure plane (M1) a second metallization plane (M2) havinga first and a second adjacent interconnect (LBA; LBB); a firstintermediate dielectric (ILD1) for mutual electrical insulation of thefirst substructure plane (M1) and second metallization plane (M2); andvia holes (V) filled with a conductive material (FM) in the intermediatedielectric (ILD1) for connecting the first substructure plane (M1) andsecond metallization plane (M2); a liner layer (L) made of a dielectricmaterial being provided under the second metallization plane (M2), whichliner layer is interrupted in the interspace (O) between the first andsecond adjacent interconnects (LBA; LBB) of the second metallizationplane (M2).
 2. The metallization arrangement as claimed in claim 1,wherein the first substructure plane (M1) is a first metallizationplane.
 3. The metallization arrangement as claimed in claim 1 or 2,wherein the interspace (O) between the first and second adjacentinterconnects (LBA; LBB) of the second metallization plane (M2) isfilled with a second intermediate dielectric (ILD2) above the firstintermediate dielectric (ILD1).
 4. The metallization arrangement asclaimed in claim 1, 2 or 3, wherein the semiconductor structure has anelectrical circuit integrated in a silicon substrate.
 5. Themetallization arrangement as claimed in one of claims 1 to 4, whereinthe liner layer (L) is fabricated from silicon dioxide or siliconnitride.
 6. The metallization arrangement as claimed in one of claims 2to 4, wherein the first and/or second metallization plane (M1; M2)are/is fabricated from ALCu.
 7. A method for fabricating a metallizationarrangement for a semiconductor structure (1) having the steps of:providing a first substructure plane (M1), preferably a firstmetallization plane, on the semiconductor structure (1); providing firstintermediate dielectric (ILD1) on the first substructure plane (M1);providing a liner layer (L) made of a dielectric material on the firstsubstructure plane (M1); providing via holes (V) filled with aconductive material (FM) in the first intermediate dielectric (ILD1) andthe liner layer (L); providing a second metallization plane (M2) on theresulting structure; patterning a first and a second adjacentinterconnect (LBA; LBB) in the second metallization plane (M2); andinterrupting the liner layer in the interspace (O) between the first andsecond adjacent interconnects (LBA; LBB) of the second metallizationplane (M2).
 8. The method as claimed in claim 7, wherein the patterningand interrupting are carried out in a common etching step.
 9. The methodas claimed in claim 7 or 8, wherein the semiconductor structure has anelectrical circuit integrated in a silicon substrate.
 10. The method asclaimed in claim 9, wherein the liner layer (L) is fabricated fromsilicon dioxide or silicon nitride.
 11. The method as claimed in claim10, wherein the patterning is carried out in a first metal etching stepand the interrupting is carried out in a second silicon dioxide etchingstep.
 12. The method as claimed in one of claims 7 to 11, wherein theinterspace (O) between the first and second adjacent interconnects (LBA;LBB) of the second metallization on plane (M2) is filled with a secondintermediate dielectric (ILD2) above the first intermediate dielectric(ILD1).
 13. The method as claimed in one of claims 7 to 12, wherein ahard mask or a resist mask, which is provided on the secondmetallization plane (M2), is used for the patterning and interruptingprocesses.